The present invention relates to a semiconductor integrated circuit device such as a processor, and more particularly to a microprocessor which is capable of realizing the high speed operation as well as the low power consumption by controlling substrate biases of a processor circuitry constituted by MOS transistors in accordance with an operation mode of the processor.
At the present time, for realization of a microprocessor, an integrated circuit employing CMOSs is widely used. The power consumption of the CMOS circuit is classified into the dynamic power consumption due to charge and discharge during the switching, and the static power consumption due to a leakage current. Out of them, since the dynamic power consumption is proportional to a power source voltage Vdd squared and hence occupies the large power consumption, in order to promote the low power consumption, it is effective to reduce the power source voltage. Then, in recent years, the power source voltages of many microprocessors have been reduced.
As for the present low power consumption type microprocessor, there is known the microprocessor which includes the power management mechanism and which has a plurality of operation modes provided therein and in accordance therewith, stops the supply of a clock to execution units during the stand-by. By stopping the clock supply, the dynamic power consumption due to the switching in the unnecessary units can be reduced as much as possible. However, the static power consumption due to the leakage current can not be reduced and hence still remains.
Since the operation speed of the CMOS circuit is decreased along with reduction of the power source voltage, in order to prevent the degradation of the operation speed, the threshold voltage of the MOS transistor needs to be reduced in conjunction with the reduction of the power supply voltage. However, since if the threshold voltage is reduced, then the leakage current is remarkably increased, along with the reduction of the power source voltage, the increase of the static power consumption due to the leakage current which was not conventionally large so much becomes remarkable. For this reason, it becomes a problem to realize a microprocessor in which the high speed is compatible with the low power consumption.
As for a method of solving the problem associated with both the operation speed and the leakage current of the MOS transistor circuit, a method wherein the threshold voltage of the MOS transistor is controlled by setting variably the substrate biases is disclosed in JP-A-6-53496.
The description will hereinbelow be given with respect to the device structure for use in setting variably the substrate biases with reference to FIG. 2. FIG. 2 shows a cross sectional view of a circuit having the CMOS structure. As shown in the figure, an n type well 205 is formed in a part of a surface layer of a p type well (p type substrate) 201, an n-channel MOS transistor consisting of an n+ type source/drain region 202, a gate oxide film 203 and a gate electrode 204 is formed on a surface of the p type well 201, and a p-channel MOS transistor consisting of a p+ type source/drain region 206, a gate oxide film 207 and a gate electrode 208 is formed on a surface of the n type well 205.
Normally, the source of the p-channel MOS transistor and the source of the n-channel MOS transistor are respectively connected to the power source voltage (hereinafter, referred as Vdd) and the ground electric potential (hereinafter, referred as Vss), and the drains of the n-channel MOS transistor and the p-channel MOS transistor are connected to the output signal. As for terminals through which the substrate biases are given, Vbp 209 is provided in the n type well 205 of the p-channel MOS transistor, and Vbn 210 is provided in the p type well 201 of the n-channel MOS transistor.
While when employing the device as shown in FIG. 2, normally, Vbp 209 is connected to Vdd and Vbn 210 is connected to Vss, during the non-operation of the circuits, these substrate biases are switched so that Vbp 209 is connected to the higher electric potential and Vbn 210 is connected to the lower electric potential, whereby the threshold voltages of the MOS transistors can be increased and hence the leakage current can be reduced.
In order to realize a microprocessor in which the high speed operation is compatible with the low power consumption, it is required that for the processor circuitry, the variable control of the substrate biases as described above is carried out, and during the operation of the processor, the threshold voltages of the MOS transistors are decreased to maintain the high speed operation, while during the stand-by thereof, the threshold voltages are increased to reduce the leakage current. However, in order to control variably the substrate biases of the processor, the timing of reactivating the processor in the proceeding of the operation mode of the processor when switching the substrate biases, in particular in the proceeding of the operation mode from the stand-by state to the operation state is accurately controlled, whereby the malfunction of the processor must be prevented.
The present invention was made in order to solve the above-mentioned problems, and it is therefore an object of the present invention to provide a high speed and low power consumption processor by realizing the above-mentioned substrate bias control, on a processor chip, which is applied to the various operation modes of the processor.
In order to solve the above-mentioned problems, a feature of the present invention is provided by providing: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
In addition, another feature of the processor according to the present invention is that a semiconductor device of the processor chip has a triple well structure, and also the processor main circuit is formed on a well region different from those of the substrate bias switching unit and the operation mode control unit.
In addition, still another feature of the processor according to the present invention is that the operation mode control unit includes, as means for waiting, before restarting the operation of the processor main circuit when switching the biases, until the bias voltages switched thereto are stabilized, either an on-chip timer for measuring a lapse of the time period required for stabilizing the biases, or a sensor for detecting that the biases have been stabilized to predetermined voltages.
In addition, yet another feature of the processor according to the present invention is provided by providing:
the processor main circuit in which the semiconductor device of the processor chip has a triple well structure and is divided into a plurality of functional modules which are respectively formed on the different wells; a substrate bias switching unit for switching the substrate biases to the substrate of the respective functional modules; a operation mode control unit for controlling, in response to execution to make stand-by one functional module or the plurality of functional modules in the processor main circuit, the substrate bias switching unit in such a way that the substrate biases of the one functional module or the plurality of functional modules are switched over to the voltages for the stand-by mode, and for controlling, when having received a signal to release the stand-by mode of the one functional module or the plurality of functional modules from the outside or the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to the voltages for a normal mode, and also for informing, after the bias voltages switched thereto have been stabilized, the processor main circuit of that the stand-by of the one functional module or the plurality of functional modules has been released.
In addition, a further feature of the processor according to the present invention is provided by providing: means for switching dynamically the operation speed of the processor main circuit; and an operation mode control unit for controlling, in response to execution of an instruction to change the operation frequency in the processor main circuit, the substrate bias switching unit in such a way that the substrate biases of the processor main circuit or the functional modules are switched to voltages which are suitable for the operation frequency thereof, and for informing, after the bias voltages switched thereto have been stabilized, the processor main circuit of that the switching of the operation speed has been completed.
Further, an even further feature of the processor according to the present invention is that the substrate bias switching unit is constituted by a substrate bias generating circuit for generating therein the voltages of the substrate biases.
In addition, the present invention also proposes a control method contributing to the promotion of the low power consumption of the device. That is, since while the transistor having the low threshold is operated at a high speed, the leakage current passing between the source and the drain is large to increase the power consumption, it is important to prevent the large leakage current there-between.
As for the construction therefor, there is provided a control method of controlling the power consumption of a semiconductor integrated circuit device including a plurality of element circuit blocks having transistors formed on a semiconductor substrate and being operated on the basis of a clock signal, wherein a first mode in which all the element circuit blocks are operated on the basis of the clock signal, a second mode in which the supply of the clock signal to at least one of the element circuit blocks is stopped, and a third mode in which the supply of the clock signal to all the element circuit blocks is stopped and also substrate biases of at least part of the transistors formed on the semiconductor substrate are controlled to increase thresholds of the associated transistors are switched to be used.
A main circuit is, for example, a processor including a CPU and the like. The first mode is a mode wherein the main circuit carries out the normal operation (computing, storage or the like).
The second mode is a state in which the supply of the clock to a part of the processor is stopped, and is called a sleep mode, a deep sleep mode or the like for example. By selecting the range in which the clock is stopped, it is possible to promote the low power consumption while maintaining only the necessary functions.
The third mode is a mode wherein the substrate biases are controlled for the circuits of the processor so as to increase the thresholds of the transistors constituting the circuits to reduce the power consumption due to the sub-threshold leakage current, and is referred to as a stand-by mode or a hardware stand-by mode for example. While the operation mode can be returned from the stand-by mode to the normal state by the interruption control, in the hardware stand-by mode, the operation mode can be returned thereto by only the reset. In the third mode, the functions of the main circuit are stopped.
As for the construction of the overall circuitry, the element circuit blocks are included in a first circuit block, and the clock signal is formed from an oscillation circuit included in a second circuit block, and the clock signal and the information signals which are to be processed in the first circuit block are inputted from the second circuit block to the first circuit block. In addition to the oscillation circuit, an I/O circuit, and a control circuit for controlling the substrate biases are included in the second circuit block. Normally, the high speed operation is not required for the second circuit block so much as for the first circuit block. Then, it is desirable that the thresholds of the transistors constituting the second circuit block are larger than those of the transistors constituting the first circuit block and also the operation voltages of the former are higher than those of the latter. In addition, the transistors constituting the main circuit of the first circuit block are formed on the well different from those of other circuits, whereby the influence of other circuits thereupon can be reduced.
When the operation voltages of the first circuit block are different from those of the second circuit block, level conversion circuits are required to be provided between the first and second circuit blocks. For example, in order to carry out the conversion of the signal level, a level-down circuit is provided in the first circuit block, while a level-up circuit is provided in the second circuit block.
Since in the present invention, by switching the mode of the interest over to another mode, the substrate bias voltages are dynamically switched, in order to ensure the reliability, the operation sequence thereof is important.
When switching the operation mode from the first or second mode to the third mode, firstly, the clock signal which is inputted from the second circuit block to the first circuit block, and the information signals which are inputted to the first circuit block in order to be processed therein are stopped, and next, the substrate biases of at least part of the transistors formed on the semiconductor substrate are controlled to increase the thresholds of the associated transistors. As a result, the input to the first circuit block in the state in which the operation of the first circuit block is unstable can be blocked and also the malfunction of the first circuit block can be prevented.
For this operation, the procedure may be adopted in which after the signal inputs to the first circuit block are stopped and the device waits for a predetermined time period (e.g., 60 xcexc sec. or so) through a timer or the like, the substrate biases are controlled. The timer for waiting is provided in the outside of the first circuit block, e.g., either in the second circuit block or in the outside of the device.
In addition, when switching the operation mode from the third mode (stand-by mode) to the first mode, the substrate biases of at least part of the transistors formed on the semiconductor substrate are controlled to decrease the thresholds of the associated transistors, and next, the input of the above-mentioned clock signal which is inputted from the second circuit block to the first circuit block and the information signals which are to be processed in the first circuit block is started. That is, in order to prevent the malfunction of the first circuit block, after the substrate voltages of the first circuit block have been stabilized, the input of the signals is started.
For this reason, when switching the operation mode from the third mode to the first mode, after the substrate biases of the first circuit block are controlled to decrease the thresholds of the associated transistors and the device waits for a predetermined time period by the timer so that the operation is stabilized, the input of the clock signal which is to be inputted to the first circuit block and other signals is started.
Another method is such that after the state of the thresholds of the transistors have been confirmed by a voltage monitor or the like, the signal input to the first circuit block is started. Or, on the basis of the state of a substrate bias generating circuit for controlling the substrate voltages, in accordance with the signal which is outputted from the substrate bias generating circuit in order to report the stand-by release, the input of the clock signal and other signals which are to be inputted to the first circuit block is started.
As for a method of stopping the information signals and the clock signal to the first circuit block, it is considered that the signal levels are fixed by an output fixing circuit (level holding circuit) provided in the second circuit block. In the first mode, while the signals are inputted to the level-down circuit through the output fixing circuit, in the third mode, the inputs to the level-down circuit are fixed.